As a test method with reduced data volume of test patterns for testing a logic circuit, a Built-In Self-Test (BIST) is known. BIST utilizes a test pattern generation device for generating a new test pattern from an original test pattern. Here, in general, there is trade-off relation between increase of fault coverage of a test pattern and shift power reduction of the test pattern during test. So far, test pattern generation devices or the like have been developed balancing the increase of fault coverage and shift power reduction (See Non Patent Literature 1).
FIG. 16 shows a schematic diagram of a circuit of a test pattern generation device described in Non Patent Literature 1. The test pattern generation device described in Non Patent Literature 1 generates a new logic value from capture output values outputted when the last generated test vector is inputted into a circuit under test. First, the test pattern generation device extracts the last 2 bits from the capture output values outputted when the last generated test vector is inputted into the circuit under test. If the logic values of the extracted 2 bits are different, shift-in is executed without changing the values previously inputted into the scan chain. If the logic values of the extracted 2 bits are the same, a new logic value is inputted. Like this, the test pattern generation device executes shift-in with/without reversing the value outputted from LFSR, referring the comparison result between the last 2 bits of the capture output values outputted when the last generated test vector is inputted into a circuit under test.